View MSM80C88A-10JS_2973963.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/37 ? semiconductor msm80c88a-10rs/gs/js general description the msm80c88a-10 is internal 16-bit cpus with 8-bit interface implemented in silicon gate cmos technology. it is designed with the same processing speed as the nmos8088-1, but with considerably less power consumption. the processor has attributes of both 8 and 16-bit microprocessor. it is directly compatible with msm80c86a-10 software and msm80c85ah hardware and peripherals. features ? 8-bit data bus interface ? 16-bit internal architecture ? 1 mbyte direct addressable memory space ? software compatible with msm80c86a-10 ? internal 14-word by 16-bit register set ? 24-operand addressing modes ? bit, byte, word and string operations ? 8 and 16-bit signed and unsigned arithmetic operation ? from dc to 10 mhz clock rate (note) ? low power dissipation (10ma/mhz) ? bus hold circuitry eliminated pull-up resistors ? 40-pin plastic dip (dip 40-p-600-2.54): (product name: msm80c88a-10rs) ? 44-pin plastic qfj (qfj44-p-s650-1.27): (product name: MSM80C88A-10JS) ? 56-pin plastic qfp (qfp56-p-1519-1.00-k): (product name: msm80c88a-10gs-k) (note) 10 mhz spec. is not compatible with intel 8088-1 spec. ? semiconductor msm80c88a-10rs/gs/js 8-bit cmos microprocessor e2o0011-27-x2 this version: jan. 1998 previous version: aug. 1996
2/37 ? semiconductor msm80c88a-10rs/gs/js functional block diagram ss 0 exeuction unit register file relocation register file data pointer and index registers (8 words) segment registers and instruction pointer (5 words) 16bit alu flags bus interface unit ad 7 - ad 0 inta , rd , wr , io/ m dt/ r , den , ale 12 8 4 3 4-byte instruction queue lock qs 0 , qs 1 s 2 , s 1 , s 0 gnd v cc 2 3 3 mn/ mx ready reset clk test intr nmi rq /gt 0 , 1 hold hlda 2 control & timing bus interface unit a 19 / s 6 a 8 . . .
3/37 ? semiconductor msm80c88a-10rs/gs/js pin configuration (top view) 40 pin plastic dip 16 15 14 13 gnd 20 19 18 17 gnd 1 2 3 4 5 6 7 8 9 10 11 12 32 31 30 29 28 27 26 37 38 39 40 36 35 34 33 25 reset a 15 a 16 /s 3 a 17 /s 4 a 18 /s 5 a 19 /s 6 ss 0 (high) mn/ mx rd hold( rq / gt0 ) hlda( rq / gt1 ) wr(lock) io/ m (s 2 ) dt/ r (s 1 ) den (s 0 ) ale(qs 0 ) inta (qs 1 ) test ready 24 23 22 21 v cc nmi intr clk a 9 a 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 ad 1 ad 0 a 14 a 13 a 12 a 11 a 10 56 a 11 nc hold( rq / gt0 ) nc 42 41 40 39 38 37 36 nc a 19 /s 6 ss 0 (high) mn/ mx rd 35 34 33 32 31 30 29 nc hlda( rq / gt1 ) wr ( lock ) io/ m (s 2 ) dt/ r (s 1 ) den (s 0 ) 1 2 3 4 5 6 7 nc a 10 a 9 a 8 ad 7 ad 6 nc 8 9 10 11 12 13 14 nc ad 5 ad 4 ad 3 ad 2 ad 1 ad 0 56 pin plastic qfp 39 38 37 36 35 34 33 nc a19/s6 high fix( ss0 ) mn/ mx rd hold( rq / gt0 ) hlda( rq / gt1 ) a 10 a 9 a 8 ad 7 ad 6 ad 5 ad 4 18 19 20 21 22 23 24 nc nm1 intr clk gnd nc reset 6 5 4 3 2 1 44 a 11 a 12 a 13 a 14 gnd nc 7 8 9 10 11 12 13 32 31 30 29 wr ( lock ) m/ io (s 2 ) dt/ r (s 1 ) ad 3 ad 2 ad 1 ad 0 14 15 16 17 den (s 0 ) v cc 25 26 27 28 ready test ( inta )qs 1 (ale)qs 0 43 42 41 40 a 15 a 16 /s 3 a 17 /s 4 a 18 /s 5 44 pin plastic qfj 55 a 12 54 a 13 53 a 14 52 nc 51 gnd 50 nc 49 v cc 48 v cc 47 nc 46 a 15 45 a 16 /s 3 44 a 17 /s 4 43 a 18 /s 5 15 nmi 16 intr 17 clk 18 nc 19 nc 20 gnd 21 v cc 22 nc 23 nc 24 reset 25 ready 26 test 27 inta (qs 1 ) 28 ale(qs 0 )
4/37 ? semiconductor msm80c88a-10rs/gs/js absolute maximum rating C65 to +150 msm80c88a-10rs power supply voltage v cc C0.5 to +7 v input voltage v in C0.5 to v cc +0.5 v output voltage v out C0.5 to v cc +0.5 v storage temperature t stg c power dissipation p d 0.7 w parameter units symbol with respect to gnd ta = 25c condition rating msm80c88a-10gs MSM80C88A-10JS 1.0 operating range range power supply voltage v cc 4.75 to 5.25 v operating temperature t op 0 to +70 c parameter unit symbol recommended operating conditions typ. power supply voltage v cc 5.0 v t op +25 "l" input voltage v il v il "h" input voltage *1 min. 4.75 0 C0.5 v cc -0.8 max. 5.25 +70 +0.8 v cc +0.5 parameter unit symbol c v v *2 2.0 v cc +0.5 v operating temperature *1 only clk *2 except clk
5/37 ? semiconductor msm80c88a-10rs/gs/js dc characteristics max. "l" output voltage v ol 0.4 v "h" output voltage v oh v parameter unit symbol min. 3.0 v cc C0.4 i ol = 2.5 ma i oh = C2.5 ma i oh = C100 m a conditions input leak current i li +1.0 m a output leak current i lo +10 m a C1.0 C10 0 v in v cc v o = v cc or gnd typ. input leakage current (bus hold low) i bhl 400 m a 50 v in = 0.8 v *3 input leakage current (bus hold high i bhh C400 m a C50 v in = 3.0 v *4 bus hold low overdrive i bhlo 600 m a *5 bus hold high overdrive i bhho C600 m a *6 operating power supply current i ccs 10 standby power current i cc 500 v il = gnd v ih = v cc v in = v cc or gnd outputs unloaded clk = gnd or v cc ma/mhz m a input capacitance c in 10 pf output capacitance c out 15 pf i/o capacitance c i/o 20 pf *7 *7 *7 (v cc = 4.5 to 5.5 v, ta = C40c to +85c) *3 test conditions are to lower v in to gnd and then raise v in to 0.8 v on pins 2-16, and 35-39. *4 test conditions are to raise v in to v cc and then lower v in to 3.0 v on pins 2-16, 26-32, and 34- 39. *5 an external driver must source at least i bhlo to switch this node from low to high. *6 an external driver must sink at least i bhho to switch this node from high to low. *7 test conditions: a) freq = 1 mhz. b) ummeasured pins at gnd. c) v in at 5.0 v or gnd.
6/37 ? semiconductor msm80c88a-10rs/gs/js ac characteristics minimum mode system timing requirements parameter symbol unit max. min. 10 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c data in setup time t dvcl 20 ns data in hold time t cldx 10 ns max. min. 8 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c 20 10 max. min. 5 mhz spec. v cc = 4.5 v to 5.5 v ta = -40 to +85c 30 10 clk rise time (from 1.0 v to 3.5 v) t ch1ch2 10ns 10 10 clk fall time (from 3.5 v to 1.0 v) t cl2cl1 10ns 10 10 clk cycle period t clcl 100 dc ns clk low time t clch 46 ns clk high time t chcl 44 ns 125 dc 68 44 200 dc 118 69 ready setup time into msm80c88a-10 t ryhch 46 ns ready hold time into msm80c88a-10 t chryx 20 ns 68 20 118 30 rdy setup time into msm 82c84a-2 (see notes 1, 2) t r1vcl 35 ns 35 35 rdy hold time into msm 82c84a-2 (see notes 1, 2) t clr1x 0ns 0 0 hold setup time t hvch 20 ns 20 35 ready inactive to clk (see note 3) t rylcl C8 ns C8 C8 t ihil 15ns 15 15 intr, nmi, test setup time (see note 2) t invch 15 ns 15 30 input rise time (except clk) (from 0.8 v to 2.0 v) t ilih 15ns 15 15 input fall time (except clk) (from 2.0 v to 0.8 v)
7/37 ? semiconductor msm80c88a-10rs/gs/js timing responses rd inactive delay t clrh 10 60 ns rd inactive to next address active t rhav t clcl -35 ns hlda valid delay t clhav 10 60 ns 10 80 t clch -40 10 100 10 150 t clch -45 10 160 rd width t rlrh 2t clcl -40 ns 2t clcl -50 2t clcl -75 wr width t wlwh 2t clcl -35 ns 2t clcl -40 2t clcl -60 address valid to ale low t aval t clch -35 ns t clch -40 t clch -60 ouput rise time (from 0.8 v to 2.0 v) t oloh 15ns 15 15 output fall time (from 2.0 v to 0.8 v) t ohol 15ns 15 15 parameter symbol unit max. min. 10 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c max. min. 8 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c max. min. 5 mhz spec. v cc = 4.5 v to 5.5 v ta = C40 to +85c address valid delay t clav 10 60 ns address hold time t clax 10 ns address float delay t claz t clax 50 ns 10 60 10 t clax 50 10 110 10 t clax 80 ale width t lhll t clch -10 ns t clch -10 t clch -20 ale active delay t cllh 40ns 50 80 ale inactive delay t chll 45ns 55 85 address hold time to ale inactive t llax t clch -10 ns t clch -10 t clch -10 data valid delay t cldv 10 60 ns 60 10 110 data hold time t chdx 10 ns 10 data hold time after wr t whdx t clch -25 ns t clch -30 t clch -30 control active delay 1 t cvctv 10 55 ns 10 70 10 110 control active delay 2 t chctv 10 50 ns 10 60 10 110 control inactive delay t cvctx 10 55 ns 10 70 10 110 address float to rd active t azrl 0ns 0 0 rd active delay t clrl 10 70 ns 10 100 10 165 notes: 1. signals at msm82c84a-2 shown for reference only. 2. setup requirement for asynchronous signal only to guarantee recognition at next clk. 3. applies only to t 2 state. (8 ns into t 3 )
8/37 ? semiconductor msm80c88a-10rs/gs/js maximum mode system (using msm82c88-2 bus controller) timing requirements parameter symbol unit max. min. 10 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c data in setup time t dvcl 20 ns data in hold time t cldx 10 ns max. min. 8 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c 20 10 max. min. 5 mhz spec. v cc = 4.5 v to 5.5 v ta = C40 to +85c 30 10 clk rise time (from 1.0 v to 3.5 v) t ch1ch2 10ns 10 10 clk fall time (from 3.5 v to 1.0 v) t cl2cl1 10ns 10 10 clk cycle period t clcl 100 dc ns clk low time t clch 46 ns clk high time t chcl 44 ns 125 dc 68 44 200 dc 118 69 ready setup time into msm80c88a-10 t ryhch 46 ns ready hold time into msm80c88a-10 t chryx 20 ns 68 20 118 30 rdy setup time into msm 82c84a-2 (see notes 1, 2) t r1vcl 35 ns 35 35 rdy hold time into msm82c84a-2 (see notes 1, 2) t clr1x 0ns 0 0 ready inactive to clk (see note 3) t rylcl C8 ns C8 C8 t ihil 15ns 15 15 input rise time (except clk) (from 0.8 v to 2.0 v) t ilih 15ns 15 15 input fall time (except clk) (from 2.0 v to 0.8 v) rq / gt setup time t gvch 15 ns 15 30 rq hold time into msm80c88a-10 t chgx 20 ns 30 40 setup time for recognition (nmi, intr, test ) (see note 2) t invch 15 ns 15 30
9/37 ? semiconductor msm80c88a-10rs/gs/js timing responses parameter symbol unit max. min. 10 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c max. min. 8 mhz spec. v cc = 4.75 v to 5.25 v ta = 0 to +70c max. min. 5 mhz spec. v cc = 4.5 v to 5.5 v ta = C40 to +85c command active delay (see note 1) t clml 535ns command inactive delay (see note 1) t clmh 545ns ready active to status passive (see note 4) t ryhsh 45ns 535 545 65 5 45 5 45 110 status inactive delay status active delay t chsv 10 45 ns 10 60 10 110 address valid delay t clsh 10 60 ns 10 70 10 130 address hold time t clav 10 60 ns 10 60 10 110 address float delay t clax 10 ns 10 10 status valid to ale high (see note 1) t claz t clax 50 ns t clax 50 t clax 80 status valid to mce high (see note 1) t svlh 25ns 25 35 clk low to ale valid (see note 1) t svmch 30ns 30 35 clk low to mce high (see note 1) t cllh 25ns 25 35 ale inactive delay (see note 1) t clmch 25ns 25 35 data valid delay t chll 425ns 425 4 35 data hold time t cldv 10 60 ns 10 60 10 110 t chdx 10 ns 10 10 control active delay (see note 1) t cvnv 545ns control inactive delay (see note 1) t cvnx 545ns 545 545 5 45 5 45 rd active delay address float to rd active t azrl 0ns 0 0 rd inactive delay t clrl 10 70 ns 10 100 10 165 rd inactive to next address active t clrh 10 60 ns 10 80 10 150 t rhav t clcl -35 ns t clcl -40 t clcl -45 t chdtl 50ns 50 50 gt active delay (see note 5) gt inactive delay t clgl 045ns 050 0 85 rd width t clgh 045ns 050 0 85 output rise time (from 0.8 v to 2.0 v) t rlrh 2t clcl -40 ns 2t clcl -50 2t clcl -75 output fall time (from 2.0 v to 0.8 v) t oloh 15ns 15 15 t ohol 15ns 15 15 direction control active delay (see note 1) t chdth 30ns 30 35 direction control inactive delay (see note 1) notes: 1. signals at msm82c84a-2 or msm82c88-2 are shown for reference only. 2. setup requirement for asynchronous signal only to guarantee recognition at next clk. 3. applies only to t 2 state (8 ns into t 3 ) 4. applies only to t 3 and wait states. 5. c l = 40 pf ( rq / gt 0 , rq / gt 1 )
10/37 ? semiconductor msm80c88a-10rs/gs/js a.c. testing input, output waveform a.c. testing load circuit test points 1.5 0.45 1.5 2.4 a.c. testing: inputs are driven at 2.4 v for a logic "1" and 0.45 v for a logic "0" timing measurements are 1.5 v for both a logic "1" and "0". c l = 100 pf c l includes jig capacitance. device under test timing chart minimum mode v ih v il io/ m , ss 0 a 19 /s 6 - a 16 /s 3 ale rdy (msm82c84a-2 input) see note 4 ready (msm80c88a-10 input) read cycle (note 1) ( wr , inta = v oh ) ad 7 - ad 0 rd dt/ r den t chctv t chcl t clcl t ch1ch2 t cl2cl1 t 1 t 2 t 3 tw t 4 t clch t chdx t cldv t clax t clav t cllh t lhll t llax t aval t chll t r1vcl a 19 - a 16 s 6 - s 3 t clr1x t rylcl t chryx t ryhch t cldx t dvcl t claz t clax t clav ad 7 - ad 0 t azrl t chctv t clrl t cvctv t cvctx t rlrh t chctv t clrh t rhav data in float a 15 - a 8 (float during inta) v ih v il clk (msm82c84a-2 output) a 15 - a 8 t llax t aval float
11/37 ? semiconductor msm80c88a-10rs/gs/js minimum mode (continued) notes: 1. all signals switch between v oh and v ol unless otherwise specified. 2. rdy is sampled near the end of t 2 , t 3 , tw to determine if tw machines states are to be inserted. 3. two inta cycles run back-to-back. the msm80c88a-10 local addr/data bus is floating during both inta cycles. control signals shown for second inta cycle. 4. signals at msm82c84a-2 shown for reference only. 5. all timing measurements are made at 1.5 v unless otherwise noted. v ih v il io/ m , ss 0 a 19 /s 6 - a 16 /s 3 ale ad 7 - ad 0 den wr ad 7 - ad 0 dt/ r inta den write cycle (note 1) rd , inta dt/ r = v oh inta cycle (notes 1 & 3) ( rd , wr = v oh bhe = v ol ) clk (msm82c84a-2 output) t clcl t chctv t chcl t ch1ch2 t cl2cl1 t 2 t 3 t 4 t w t clch t clav t cllh t clax t cldv t chdx a 19 - a 16 s 6 - s 3 t lhll t llax t aval t cldv t clav t cvctv t llax t aval t cvctv t wlwh t claz t chctv t cvctv t cvctv t cvctx t clav t chctv t cldx t cvctx t dvcl t cvctx t chdx ad 7 - ad 0 data out float pointer float invalid address software halt rd , wr , inta = v oh dt/ r = indeterminate t clax t whdx software halt t clav t chll
12/37 ? semiconductor msm80c88a-10rs/gs/js maximum mode v ih v il qs 0 , qs 1 a 19 /s 6 - a 16 /s 3 s 2 , s 1 , s 0 (except halt) ale (msm82c88-2 output) rdy (msm82c84a-2 input) see note 5 ready (msm80c88a-10 input) read cycle ad 7 - ad 0 rd mrdc or iorc den dt/ r msm82c88-2 outputs see notes 5, 6 t clav t clcl t ch1ch2 t cl2cl1 t w t 1 t 2 t 3 t 4 t chcl t clch t chsv t clsh t clav t clax t cldv t chdx t svlh t cllh t chll t rylcl t r1vcl t clr1x t chryx t ryhsh t ryhch t claz t dvcl t rhav t chdth t clmh t cvnx t rlrh t cvnv t clml t clrl t chdtl t clav t clrh t cldx t azrl a 19 - a 16 (see note 8) data in float ad 7 - ad 0 a 15 - a 8 s 6 - s 3 float v ih v il t clax clk (msm82c84a-2 output) a 15 - a 8
13/37 ? semiconductor msm80c88a-10rs/gs/js maximum mode (continued) notes: 1. all signals switch between v oh and v ol unless otherwise specified. 2. rdy is sampled near the end of t 2 , t 3 , t w to determine if t w machines states are to be inserted. 3. cascade address is valid between first and second inta cycle. 4. two inta cycles run back-to-back. the msm80c86a-10 local addr/data bus is floating during both inta cycles. control for pointer address is shown for second inta cycle. 5. signal at msm82c84a-2 or msm82c88-2 shown for reference only. the issuance of the msm82c88-2 command and control signals ( mrdc , mwtc , amwc , iorc , iowc , aiowc , inta and den ) lags the active high msm82c88-2 cen. 7. all timing measurements are made at 1.5 v unless otherwise noted. 8. status inactive in state just prior to t 4 . v ih v il ad 7 - ad 0 a 15 - a 8 (see notes 3 & 4) clk (msm82c84a-2 outputs) s 2 , s 1 , s 0 (except halt) msm82c88-2 outputs see notes 5, 6 msm82c88-2 outputs see notes 5, 6 inta cycle t chsv t 1 den anmc or aiowc mwtc or iowc mce/ pden ad 7 - ad 0 dt/ r inta den write cycle ad 7 - ad 0 , a 15 - a 8 s 2 , s 1 , s 0 software halt ( den v ol ; rd , mr dc , iorc, mwt c , amw c , iow c , aiowc , inta v oh ) t clav t clsh t clax t cldv t cvnx t clml t clmh t clml t clmh t dvcl t cldx t chdth t clmh t cvnx t cvnv t clav t clml t chdtl t clmch t svmch t cvnx t claz t cvnv data (see note 8) pointer float float float reserved for cascade addr float ad 7 - ad 0 t 2 t 3 t w t 4 invalid address t chdx
14/37 ? semiconductor msm80c88a-10rs/gs/js asynchronous signal recognition hold/hold acknowledge timing (minimum mode only) request/grant sequence timing (maximum mode only) clk signal nmi intr test t invch (see note 1) note: 1 setup requirements for asynchronous signals only to guarantee recognition at next clk bus lock signal timing (maximum mode only) reset timing clk lock t clav any clk cycle any clk cycle t clav 3 50 m sec t dvcl clk t cldx reset v cc 3 4 clk cycles clk hold ad 7 - ad 0 , a 15 - a 8 a 19 /s 6 - a 16 /s 3 rd io/ m dt/ r , wr , den hlda msm80c88a-10 coprocessor msm80c88a-10 1 clk cycle 1 or 2 cycles t hvch t hvch t clhav t clhav t claz any clk cycle clk rq / gt ad 7 - ad 0 , a 15 - a 8 a 19 /s 6 - a 16 /s 3 s 2 , s 1 , s 0 , rd , cock t clgh 3 t clcl t gvch t chgx t clgl 3 t clcl t clgh previous grant t claz pulse 3 coprocessor release msm80c88a-10 coprocessor msm80c88a-10 (see note 1) note: 1 the coprocessor may not drive the busses outside the region shown without risking contention pulse 1 coprocessor rq pulse 2 msm80c88 gt > 0 clk cycle
15/37 ? semiconductor msm80c88a-10rs/gs/js pin description ad 0 - ad 7 address data bus: input/output these lines are the multiplexed address and data bus. these are the address bus at t 1 cycle and the data bus at t 2 , t 3 , t w and t 4 cycle. t 2 , t 3 , t w and t 4 cycle. these lines are high impedance during interrupt acknowledge and hold acknowledge. a 8 - a 15 address bus: output these lines are the address bus bits 8 thru 15 at all cycles. these lines do not have to be latched by an ale signal. these lines are high impedance during interrupt acknowledge and hold acknowledge. a 16 /s 3 , a 17 /s 4 , a 18 /s 5 , a 19 /s 6 addres/status : output these are the four most significant address as at the t 1 , cycle. accessing i/o port address, these are low at t 1 cycle. these lines are status lines at the t 2 , t 3 , t w and t 4 cycles. s 5 indicates interrupt enable flag. s 3 and s 4 are encoded as shown below. these lines are high impedance during hold acknowledge. rd read: output this line indicates that cpu is in a memory or i/o read cycle. this line is the read strobe signal when cpu reads data from a memory or i/o device. this line is active low. this line is high impedance during hold acknowledge. ready ready:input this line indicates to the cpu that the addressed memory or i/o device is ready to read or write. this line is active high. if the setup and hold time are out of specification, an illegal operation will occur. intr interrupt request: input this line is the level triggered interrupt request signal which is sampled during the last clock cycle of instruction and string manipulations. it can be internally masked by software. this signal is active high and internally synchronized. 1 0 1 stack 0 alternate data s 3 0 1 1 0 s 4 characteristics code or none data
16/37 ? semiconductor msm80c88a-10rs/gs/js test test: input this line is examined by a "wait" instruction. when test is high, the cpu enters an idle cycle. when test is low, the cpu exits in an idle cycle. nmi non maskable interrupt: input this line causes a type 2 interrupt. nmi is not maskable. this signal is internally synchronized and needs 2-clock cycle pulse width. reset reset:input this signal causes the cpu to initialize immediately. this signal is active high and must be at least four clock cycles. clk clock: input this signal provides the basic timing for the internal circuit. mn/ mx minimum/maximum: input this signal selects the cpus operating mode. when v cc is connected, the cpu operates in minimum mode. when gnd is connected, the cpu operates in maximum mode. v cc v cc : +5v supplied. gnd ground the following pin function descriptions are for maximum mode only. other pin functions are already described. s o , s 1 , s 2 status: output these lines indicate bus status and they are used by the msm82c88-2 bus controller to generate all memory and i/o access control signals. these lines are high impedance during hold acknowledge. these status lines are encoded as shown below. 0 0 0 read i/o port 0 (low) interrupt acknowledge s 2 0 1 1 0 s 1 characteristics write i/o port halt 1 0 1 0 1 1 1 read memory 1 (high) code access 0 1 1 0 write memory passive 1 0 1 0 s 0
17/37 ? semiconductor msm80c88a-10rs/gs/js rq /gt 0 rq /gt 1 request/grant:input/output these lines are used for bus request from other devices and bus grant to other devices. these lines are bidirectional and active low. lock lock:output this line is active low. when this line is low, other devices cannot gain control of the bus. this line is high impedance hold acknowledge. qs 0 /qs 1 queue status: output these are queue status lines that indicate internal instruction queue status. 0 1 (high) 1 first byte of op code from queue 0 (low) no operation qs 1 1 0 1 0 qs 0 characteristics empty the queue subsequent byte from queue the following pin function descriptions are minimum mode only. other pin functions are already described. io/ m status: output this line selects memory address space or i/o address space. when this line is low, the cpu selects memory address space and when it is high, the cpu selects i/o address space. this line is high impedance during hold acknowledge. wr write: output this line indicates that the cpu is in a memory or i/o write cycle. this line is a write strobe signal when the cpu writes data to memory or an i/o device. this line is active low. this line is high impedance during hold acknowledge. inta interrupt acknowledge: output this line is a read strobe signal for the interrupt acknowledge cycle. this line is active low.
18/37 ? semiconductor msm80c88a-10rs/gs/js ale address latch enable: output this line is used for latching an address into the msm82c12 address latch it is a positive pulse and the trailing edge is used to strobe the address. this line is never floated. dt/ r data transmit/receive: output this line is used to control the direction of the bus transceiver. when this line is high, the cpu transmits data, and when it is low. the cpu receives data. this line is high impedance during hold acknowledge. den data enable: output this line is used to control the output enable of the bus transceiver. this line is active low. this line is high impedance during hold acknowledge. hold hold request: input this line is used for a bus request from an other device. this line is active high. hlda hold acknowledge: output this line is used for a bus grant to an other device. this line is active high. ss 0 status: output this line is logically equivalent to s 0 in the maximum mode.
19/37 ? semiconductor msm80c88a-10rs/gs/js static operation the msm80c88a-10 circuitry is of static design. internal registers, counters and latches are static and require no refresh as with dynamic circuit design. this eliminates the minimum operating frequency restriction placed on other microprocessors. the msm80c88a-10 can operate from dc to the appropriate upper frequency limit. the processor clock may be stopped in either state (high/low) and held there indefinitely. this type of operation is especially useful for system debug or power critical applications. the msm80c88a-10 can be signal stepped using only the cpu clock. this state can be maintained as long as is necessary. signal step clock operation allows simple interface circuitry to provide critical information for bringing up your system. static design also allows very low frequency operation (down to dc). in a power critical situation, this can provide extremely low power operation since 80c88a power dissipation is directly related to operating frequency. as the system frequency is reduced, so is the operating power until, ultimately, at a dc input frequency, the msm80c88a-10 power requirement is the standby current (500 m a maximum). functional description general operation the internal function of the msm80c88a-10 consists of a bus interface unit (biu) and an execution unit (eu). these units operate mutually but perform as separate processors. the biu performs instruction fetch and queueing, operand fetch, data read and write address relocation and basic bus control. by performing instruction prefetch while waiting for decoding and execution of instruction, the cpus performance is increased. up to 4-bytes for instruction stream can be queued. eu receives pre-fetched instructions from the biu queue, decodes and executes instructions and provides an un-relocated operand address to the biu. memory organization the msm80c88a-10 has a 20-bit address to memory. each address has 8-bit data width. memory is organized 00000h to fffffh and is logically divided into four segments: code, data, extra data and stack segment. each segment contains up to 64 kbytes and locates on a 16-byte boundary. (fig. 3a) all memory references are made relative to a segment register according to a select rule. memory location ffff0h is the start address after reset, and 00000h through 003ffh are reserved as an interrupt pointer. there are 256 types of interrupt pointer: each interrupt type has a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address.
20/37 ? semiconductor msm80c88a-10rs/gs/js memory organization reserved memory locations cs ss ds es segment register file xxxxoh code segment stack segment data segment extra data segment fffffh oooooh +offset 64kb reset bootstrap program jump fffffh ffffoh 3ffh 3fch 7h 4h 3h 0h interrupt pointer for type 1 interrupt pointer for type 0 interrupt pointer for type 255 minimum and maximum modes the msm80c88a-10 has two system modes: minimum and maximum. when using the maximum mode, it is easy to organize a multiple-cpu system with the msm82c88-2 bus controller which generates the bus control signal. when using the minimum mode, it is easy to organize a simple system by generating the bus control signal itself. mn/ mx is the mode select pin. definition of 24-31, 34 pin changes depends on the mn/ mx pin. stack all stack pushes and pops. memory references relative to bp base register except data references. data references when relative to stack, destination of string operation, or explicitly overridden. local data external (global data) destination of string operations: explicitly selected using a segment override. stack (cs) instructions automatic with all instruction prefetch. code (cs) memory reference need segment selection rule segment register used data (ds) extra (es)
21/37 ? semiconductor msm80c88a-10rs/gs/js bus operation the msm80c88a-10 has a time multiplexed address and data bus. if a non-multiplexed bus is desired for the system, it is only needed to add the address latch. a cpu bus cycle consists of at least four clock cycles: t 1 , t 2 , t 3 and t 4 . (fig. 4) the address output occurs during t 1 , and data transfer occurs during t 3 and t 4 . t 2 is used for changing the direction of the bus during read operation. when the device which is accessed by the cpu is not ready to data transfer and send to the cpu not ready is indicated t w cycles are inserted between t 3 and t 4 . when a bus cycle is not needed, t 1 cycles are inserted between the bus cycles for internal execution. at the t 1 cycle an ale signal is output from the cpu or the msm82c88-2 depending in mn/ mx , at the trailing edge of an ale, a valid address may be latched. status bits s 0 , s 1 and s 2 are used, in maximum mode, by the bus controller to recognize the type of bus operation according to the following table. status bits s 3 through s 6 are multiplexed with a 16 -a 19 , and therefore they are valid during t 2 through t 4 . s 3 and s 4 indicate which segment register was selected on the bus cycle, according to the following table. 0 0 0 read i/o 0 (low) interrupt acknowledge s 2 0 1 1 0 s 1 characteristics write i/o halt 1 0 1 0 1 1 1 read data from memory 1 (high) instruciton fetch 0 1 1 0 write data to memory passive (no bus cycle) 1 0 1 0 s 0 s 5 indicates interrupt enable flag. i/o addressing the msm80c88a-10 has a 64 kbyte i/o. when the cpu accesses an i/o device, addresses a 0 - a 15 are in same format as a memory access, and a 16 -a 19 are low. i/o ports addresses are same as four memory. 0 1 (high) 1 stack 0 (low) alternate data (extra segment) s 4 1 0 1 0 s 3 characteristics code or none data
22/37 ? semiconductor msm80c88a-10rs/gs/js basic system timing t 1 t 2 t 3 t twait t 4 t 1 t 2 t 3 t wait t 4 (4 + n*wait) = t cy (4 + n*wait) = t cy goes inactive in the state just prior to t 4 a 19 - a 16 a 19 - a 16 s 6 - s 3 s 6 - s 3 a 15 - a 8 a 15 - a 8 a 7 - a 0 d 7 - d 0 bus reserved for data in valid a 7 - a 0 data out (d 7 - d 0 ) ready ready wait wait memory access time clk ale s 2 , s 1 , s 0 addr/ status rd , i nta addr/ data addr ready dt/ r den wr
23/37 ? semiconductor msm80c88a-10rs/gs/js external interface reset cpu initialization is executed by the reset pin. the msm80c88a-10s reset high signal is required for greater than 4 clock cycles. the rising edge of reset terminates the present operation immediately. the falling edge of reset triggers an internal reset sequence for approximately 10 clock cycles. after internal reset sequence is finished, normal operation begins from absolute location ffff0h. interrupt operations the interrupt operation is classified as software or hardware, and hardware interrupt is classified as non-markable or maskable. an interrupt causes a new program location which is defined by the interrupt pointer table, according to the interrupt type. absolute location 00000h through 003ffh is reserved for the interrupt pointer table. the interrupt pointer table consists of 256-elements. each element is 4 bytes in size and corresponds to an 8-bit type number which is sent from an interrupt request device during the interrupt acknowledge cycle. non-maskable interrupt (nmi) the msm80c88a-10 has a non-maskable interrupt (nmi) which is of higher priority than a maskable interrupt request (intr). an nmi request pulse width needs minimum of 2 clock cycles. the nmi will be serviced at the end of the current instruction or between string manipulations. maskable interrupt (intr) the msm80c88a-10 provides another interrupt request (intr) which can be masked by software. intr is level triggerd, so it must be held until interrupt request is acknowledged. the intr will be serviced at the end of the current instruction or between string manipulations. interrupt acknowledge during the interrupt acknowledge sequence, further interrupts are disabled. the interrupt enable bit is reset by any interrupt, after which the flag register is automatically pushed onto the stack. during an acknowledge sequence, the cpu emits the lock signal from t 2 of first bus cycle to t 2 of second bus cycle. at the second bus cycle, a byte is fetched from the external device as a vector which identifies the type of interrupt. this vector is multiplied by four and used as an interrupt pointer address (intr only). the interrupt return (iret) instruction includes a flag pop operation which returns the original interrupt enable bit when it restores the flag.
24/37 ? semiconductor msm80c88a-10rs/gs/js halt when a halt instruction is executed, the cpu enters halt state. an interrupt request or reset will force the msm80c88a-10 out of the halt state. system timing C minimum mode a bus cycle begins at t 1 with an ale signal. the trailing edge of ale is used to latch the address. from t 1 to t 4 the io/ m signal indicates a memory or i/o operation. from t 2 to t 4 , the address data bus changes the address but to the data bus. the read ( rd ), write ( wr ), and interrupt acknowledge ( inta ) signals caused the addressed device to enable the data bus. these signals become active at the beginning of t 2 and inactive at the beginning of t 4 . system timing C maximum mode in maximum mode, the msm82c88-2 bus controller is added to system. the cpu sends status information to the bus controller. bus timing signals are generated by the bus controller. bus timing is almost the same as in minimum mode. interrupt acknowledge sequence ale lock inta ad 0 - ad 7 t 1 t 2 t 3 t 4 t i t 1 t 2 t 3 t 4 type vector float
25/37 ? semiconductor msm80c88a-10rs/gs/js bus hold circuitry to avoid high current conditions caused by floating inputs to cmos devices, and to eliminate the need for pull-up/down resistors, bus-hold circuitry has been used on msm80c88a-10 pins 2-16, 26-32, and 34-39 (figures 6a, 6b). these circuits will maintain the last valid logic state if no driving source is present (i.e. an unconnected pin or a driving source which goes to a high impedance state). to overdrive the bus hold circuits, an external driver must be capable of supplying approximately 400 m a minimum sink or source current at valid input voltage levels. since this bus hold circuitry is active and not a resistive type element, the associated power supply current is negligible and power dissipation is significantly reduced when compared to the use of passive pull-up resistors. input buffer exists only on i/o pins "pull-up/pull-down" input protection circuitry input buffer output driver bond pad external pin figure 6a. bus hold circuitry pin 2-16, 35-39 input buffer exists only on i/o pins p cc input protection circuitry input buffer output driver bond pad external pin "pull-up" p figure 6b. bus hold circuit pin 26-32, 34
26/37 ? semiconductor msm80c88a-10rs/gs/js mov = move: register/memory to/from register immediate to register/memory immediatye to register memory to accumulator accumulator to memory register/memory to segment register segment register to register/memory 7 1 1 1 1 1 1 1 6 0 1 0 0 0 0 0 5 0 0 1 1 1 0 0 4 0 0 1 0 0 0 0 3 1 0 w 0 0 1 1 2 0 1 0 0 1 1 1 d 1 reg 0 1 1 0 0 w w w w 0 0 7 mod mod mod mod 65 0 0 0 4 reg 0 data addr-low addr-low reg reg 3 0 21 r/m r/m r/m r/m 0 7654 data data if w = 1 addr-high addr-high 3210 7654 data if w = 1 3210 push = push: register/memory register segment register 1 0 0 1 1 0 1 0 0 1 1 reg 1 0 1 1 1 reg 1 1 0 mod 110 r/m pop = pop: register/memory register segment register 1 0 0 0 1 0 0 0 0 0 1 reg 1 1 1 1 1 reg 1 1 1 mod 000 r/m xchg = exchange: register/memory with register register with accumulator 1 1 0 0 0 0 0 1 0 0 11 reg w mod reg r/m in = input from: fixed port variable port 1 1 1 1 1 1 0 0 0 1 1 1 0 0 w w port out = output to: fixed port variable port xlat = translate byte to al lea = load ea to register lds = load pointer to ds les = load pointer to es lahf = load ah with flags sahf = store ah into flags pushf = push flags popf = pop flags 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 w w 1 1 1 0 1 0 0 1 mod mod mod reg reg reg r/m r/m r/m port data transfer
27/37 ? semiconductor msm80c88a-10rs/gs/js add = add: reg./memory with register to either immediate to register/memory immediate to accumulator 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d s 0 w w w mod mod 0 0 data reg 0 r/m r/m data data if w = 1 data if s:w = 01 adc = add with carry: reg./memory with register to either immediate to register/memory immediate to accumulator 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 d s 0 w w w mod mod 0 1 data reg 0 r/m r/m data data if w = 1 data if s:w = 01 inc = increment: register/memory register aaa = ascii adjust for add daa = decimal adjust for add 1 0 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 reg 1 1 w 1 1 mod 0 0 0 r/m sub = subtract: reg./memory with register to either immediate from register/memory immediate from accumulator 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 d s 0 w w w mod mod 1 0 data reg 1 r/m r/m data data if w = 1 data if s:w = 01 sbb = subtract with borrow: reg./memory and register to either immediate from register/memory immediate from accumulator 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 d s 0 w w w mod mod 0 1 data reg 1 r/m r/m data data if w = 1 data if s:w = 01 dec = decrement: register/memory register neg = change sign 1 0 1 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 reg 1 w w mod mod 0 0 0 1 1 1 r/m r/m cmp = compare: register/memory and register immediate with register/memory immediate from accumulator aas = ascii adjust for subtract 0 1 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 d s 0 1 w w w 1 mod mod 1 1 data reg 1 r/m r/m data data if w = 1 data if s:w = 01 arithmethic
28/37 ? semiconductor msm80c88a-10rs/gs/js das = decimal adjust for subtract mul = multiply (unsigned) imul = integer multiply (signed) aam = ascii adjust for multiply div = divide (unsigned) idiv = integer divide (signed) aad = ascii adjust for divide cbw = convert byte to word cwd = convert word to double word 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 1 w w 0 w w 1 0 1 mod mod 0 mod mod 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 r/m r/m 1 r/m r/m 1 0 0
29/37 ? semiconductor msm80c88a-10rs/gs/js not = invert shl/sal = shift logical/arithmetic left shr = shift logical right sar = shift arithmetic right rol = rotate left ror = rotate right rcl = rotate left through carry rcr = rotate right through carry 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 v v v v v v v w w w w w w w w mod mod mod mod mod mod mod mod 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 r/m r/m r/m r/m r/m r/m r/m r/m and = and: reg./memory with register to either immediate to register/memory immediate to accumulator 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 d 0 0 w w w mod mod 1 0 data reg 0 r/m r/m data data if w = 1 data if w = 1 test = and function to flags, no result: register/memory and register immediate data and register/memory immediate data and accumulator 1 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0 w w w mod mod 0 0 data reg 0 r/m r/m data data if w = 1 data if w = 1 or = or: reg./memory and register to either immediate to register/memory immediate to accumulator 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 d 0 0 w w w mod mod 0 0 data reg 1 r/m r/m data data if w = 1 data if w = 1 xor = exclusive or: reg./memory and register to either immediate to register/memory immediate to accumulator 0 1 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 d 0 0 w w w mod mod 1 1 data reg 0 r/m r/m data data if w = 1 data if w = 1 logic
30/37 ? semiconductor msm80c88a-10rs/gs/js cjmp = conditional jmp je/jz = jump on equal/zero jz/jnge = jump on less/not greater or equal jle/jng = jump on less or equal/not greater jb/jnae = jump on below/not above or equal jbe/jna = jump on below or equal/not above jp/jpe = jump on parity/parity even jo = jump on over flow js = jump on sign jne/jnz = jump on not equal/not zero jnl/jge = jump on not less/greater or equal jnle/jg = jump on not less or equal/greater jnb/jae = jump on not below/above or equal jnbe/ja = jump on not below or equal/above jnp/jpo = jump on not parity/parity odd jno = jump on not overflow jns = jump on not sigh loop = loop cx times loopz/loope = loop while zero/equal loopnz/loopne = loop while not zero equal jcxz = jump on cx zero 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp int = interrupt type specified type 3 into = interrupt on overflow iret = interrupt return 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 type rep = repeat movs = move byte/word cmps = compare byte/word scas = scan byte/word lods = load byte/word to al/ax stos = store byte/word from al/ax 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 0 1 1 0 1 z w w w w w string manipulation
31/37 ? semiconductor msm80c88a-10rs/gs/js clc = clear carry cmc = complementary carry stc = set carry cld = clear direction std = set direction cli = clear interrupt sti = set interrupt hlt = halt wait = wait esc = escape ( to external device) lock = bus lock prefix 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 0 0 1 0 x 0 0 0 0 0 0 1 1 0 1 x 0 0 1 1 0 1 0 1 0 1 x 0 mod x x x r/m processor control call = call: direct within segment indirect within segment direct intersegment indirect intersegment 7 1 1 1 1 6 1 1 0 1 5 1 1 0 1 4 0 1 1 1 3 1 1 1 1 2 0 1 0 1 1 0 1 1 1 0 0 1 0 1 7 mod mod 65 0 0 4 disp-low 1 offset-low seg-low 1 3 0 1 21 r/m r/m 0 7654 disp-high offset-high seg-high 3210 765 43210 jmp = unconditional jump: direct within segment direct within segment-short indirect within segment direct intersegment indirect intersegment 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 mod mod 1 1 disp-low disp 0 offset-low seg-low 0 0 1 r/m r/m disp-high offset-high seg-high ret = return from call: within segment within seg. adding immediate to sp intersegment intersegment adding immediate to sp 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 data-low data-low data-high dat-high control transfer
32/37 ? semiconductor msm80c88a-10rs/gs/js notes: al = 8-bit accumulator ax = 18-bit accumulator cx = count register ds = data segment ex = extra segment above/below refers to unsigned value greater=more positive less=less positive (more negative) signed value if d=1 then to reg: if d=0 then from reg. if w=1 then word instruction: if w=0 then byte instruction if mod=11 then r/m is treated as a reg field if mod=00 then disp=0*, disp-low and disp-high are absent if mod=01 then disp=disp-low sign-extended to 16 bits, disp-high is absent if mod=10 then disp=disp-high: disp-low if r/m=000 then ea=(bx)+(si)+disp if r/m=001 then ea=(bx)+(di)+disp if r/m=010 then ea=(bp)+(si)+disp if r/m=011 then ea=(bp)+(di)+disp if r/m=100 then ea=(si)+disp if r/m=101 then ea=(di)+disp if r/m=110 then ea=(bp)+disp* if r/m=111 then ea=(bx)+disp disp follows 2nd byte of instruction (before data if required) * except if mod=00 and r/m=110 then ea-disp-high: disp-low if s:w=01 then 16 bits of immediate data form the operand if s:w=11 then an immediate data byte is sign extended to form the 16-bit operand if v=0 then count=1:if v=1 then count in (cl) x=don t care z is used for string primitives for comparison with zf flag segment override prefix 001 reg 110 reg is assigned according to the following table: 16-bit (w=1) 8-bit (w=0) segment 000 ax 000 al 00 es 001 cx 001 cl 01 cs 010 dx 010 dl 10 ss 011 bx 011 bl 11 ds 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh instructions which reference the flag register file as a 16-bit object use the symbol flags to represent the file: flags=x:x:x:x:(of):(df):(if):(tf):(sf):(zf):x:(af):x:(pf):x:(cf)
33/37 ? semiconductor msm80c88a-10rs/gs/js notice on replacing low-speed devices with high-speed devices the conventional low speed devices are replaced by high-speed devices as shown below. when you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. high-speed device (new) low-speed device (old) remarks m80c85ah m80c85a/m80c85a-2 8bit mpu m80c86a-10 m80c86a/m80c86a-2 16bit mpu m80c88a-10 m80c88a/m80c88a-2 8bit mpu m82c84a-2 m82c84a/m82c84a-5 clock generator m81c55-5 m81c55 ram.i/o, timer m82c37b-5 m82c37a/m82c37a-5 dma controller m82c51a-2 m82c51a usart m82c53-2 m82c53-5 timer m82c55a-2 m82c55a-5 ppi
34/37 ? semiconductor msm80c88a-10rs/gs/js differences between msm80c88a-10 and msm80c88a-2, msm80c88a 1) manufacturing process all devices use a 1.5 m si-cmos process technology. 2) design although circuit timings of these devices are a little different, these devices have the same chip size and logics. 3) electrical characteristics oki's '96 data book for microcontroller describes that the msm80c88a-10 satisfies the electrical characteristics of the msm80c88a-2 and msm80c88a. 4) other notices 1) the noise characteristics of the high-speed msm80c88a-10 (for 10 mhz) are a little different from those of the msm80c88a-2 and msm80c88a. therefore when devices are replaced for upgrading, it is recommended to perform noise evaluation. 2) the characteristics of the msm80c88a-10 basically satisfy those of the msm80c88a-2 and msm80c88a but their timings are a little different. when critical timing is required in designing it is recommended to evaluate operating margins at various temperatures and voltages.
35/37 ? semiconductor msm80c88a-10rs/gs/js (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip40-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.10 typ.
36/37 ? semiconductor msm80c88a-10rs/gs/js (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj44-p-s650-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 2.00 typ. mirror finish
37/37 ? semiconductor msm80c88a-10rs/gs/js (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-1519-1.00-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.46 typ. mirror finish

▲Up To Search▲

Price & Availability of MSM80C88A-10JS

	To Download MSM80C88A-10JS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .